基于模糊PID控制的PCB微钻检测系统

PCB微钻的检测需要对微钻的运动轨迹进行精密的控制,这里在直线电机驱动的模型下进行研究分析。通过建立直线伺服电动机推针机构的系统仿真模型,详细分析了模糊PID算法以及数学模型。分别用传统的PID控制与模糊PID控制,对推针装置的推针过程进行了仿真。结果表明,模糊PID控制器能较好地实现微钻的位置跟踪,使其按照预定的运动轨迹运动,提高了检测的精度。     

Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors

Switched current (SI) circuits use analogue memory cells as building blocks. In these cells, like in most analogue circuits, there are hard-to-detect faults with conventional test methods. A test approach based on a built-in dynamic current sensor (BIDCS), whose detection method weights the highest frequency components of the dynamic supply current of the circuit under test, makes possible the detection of these faults, taking into account the changes in the slope of the dynamic supply current induced by the fault. A study of the influence of these faults in neighbouring cells helps to minimize the number of BICS needed in SI circuits as is shown in two algorithmic analogue-to-digital converters. Yolanda Lechuga received a degree in Industrial Engineering from the University of Cantabria (Spain) in April 2000. Since then, she has been collaborating with the Microelectronics Engineering Group at the University of Cantabria, in the Electronics Technology, Systems and Automation Engineering Department. Since October 2000 she has been a post-graduate student, to be appointed as lecturer at this university, where she is working in her Ph.D. She is interested in supply current test methods, fault simulation, BIST and design for test of mixed signal integrated circuits. Román Mozuelos received a degree in Physics with electronics from the University of Cantabria, Spain. From 1991 to 1995 he was working on the development of quartz crystal oscillators. Currently, he is a Ph.D. student and an assistant teacher at the University of Cantabria in the Department of Electronics Technology. His interests include mixed-signal design and test, fault simulation, and supply current monitoring. Miguel A. Allende received his graduate degree in 1985 and Ph.D. degree in 1994, both from the University of Cantabria, Santander, Spain. In 1996, he became an Assistant Professor of Electronics Technology at the same Institution, where he is a member of the Microelectronics Engineering Group at the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. His research interests include design of VLSI circuits for industrial applications, test and DfT in digital VLSI communication circuits, and power supply current test of mixed, analogue and digital circuits. Mar Martínez received her graduate degree and Ph.D. from the University of Cantabria (Spain) in 1986 and 1990. She has been Assistant Professor of Electronic Technology at the University of Cantabria (Spain) since 1991. At present, she is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. She has participated in several EU and Spanish National Research Projects. Her main research interest is mixed, analogue and digital circuit testing, using techniques based on supply current monitoring. She is also interested in test and design for test in digital VLSI circuits. Salvador Bracho obtained his graduate degree and Ph.D. from the University of Seville (Spain) in 1967 and 1970. He was appointed Professor of Electronic Technology at the University of Cantabria (Spain) in 1973, where, at present, he is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. He has participated, as leader of the Microelectronics Engineering Group at the University of Cantabria, in more than twenty EU and Spanish National Research Projects. His primary research interest is in the area of test and design for test, such as full scan, partial scan or self-test techniques in digital VLSI communication circuits. He is also interested in mixed-signal, analogue and digital test, using methods based on power supply current monitoring. Another research interest is the design of analogue and digital VLSI circuits for industrial applications. Prof. Bracho is a member of the Institute of Electrical and Electronic Engineers.     

基于神经网络与专家系统的压路机智能故障诊断

针对压路机发生故障时,故障原因与故障征兆之间复杂的对应关系,提出了一种基于神经网络与专家系统相结合的新方法,充分发挥了神经网络与专家系统各自的特点。介绍了系统的构成、功能及实现。利用该系统可大大提高压路机故障诊断的准确性和实时性。     

Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ

Abnormal I _DDQ (Quiescent V _DD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to enhance the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal I _DDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal I _DDQ exists in normal logic state or not.     

350MW机组短路试验时发电机差动保护误动原因分析

结合鸭河口电厂２号机组在整套 启动进行电气试验时发机差动保护出现误协问题,着重介绍了高阻型电压差动保护的原理和主要特点,通过对这一少见事件的原因分析,阐述了解决误总是的办法,为今后处理类似问题积累了经验。     

岩石边坡中断层水压的模型实验研究

该文为模型实验研究。通过自制边坡中的断层实验模型,观察、量测并分析16种不同条件时断层中不同位置的水压。模拟实验结果表明,断层中水压分布可以以线性函数拟合,此结果与Hoek理论模型相近。影响水压大小的各因素灵敏程度依次为：张裂缝中水头高度、断层倾角、充填料高度、充填料粒度、断层带厚度。     

基于遗传算法的TBDD排序方法

带时间参数的二叉判决图（ＴＢＤＤ）在电路的时滞故障测试中有着重要的应用价值，但其变量排序是用常规方法无法解决的一个优化问题。本文提出一种基于遗传算法的ＴＢＤＤ排序算法。用快速衡量值和ＴＢＤＤ节点数来计算个体的适应度。针对变量排序的特定问题，提出一种模板保序交叉方法。采用知适应的变异概率计算方法，并提出一个适合于ＴＢＤＤ排序问题的变异算法。实验结果表明较好地解决了ＴＢＤＤ的排序问题。     

粗糙集傅立叶神经网络及在故障诊断中应用

提出了粗糙集和傅立叶神经网络相结合的方法,进行粗糙集布尔逻辑离散化,并在此基础上求取初始隶属函数,以提高隶属函数准确性;再使用傅立叶神经网络进行诊断网络训练。以连续搅拌反应釜故障诊断为实例,研究结果表明,此方法可以减少网络训练时间并提高诊断精度,有效进行故障诊断。     

POWER CONSUMPTION IN MECHANICALLY AGITATED CONTACTORS USING PITCHED BLADED TURBINE IMPELLERS

Power consumption was measured in mechanically agitated contactors of internal diameter 0.3 m, 0.57 m, 1.0 m and 1.5 m. Tap water was used as a liquid in all the experiments. The impeller speed was varied in the range of 0.3-13.33 r/s. Three types of impellers, namely disc turbine (DT), pitched-blade downflow turbine (PTD) and pitched blade upflow turbine (PTU) were employed. The ratio of the impeller diameter to vessel diameter (D/T) and the ratio of impeller blade width to impeller diameter (W/D) were varied over a wide range. The effects of impeller clearance from the tank bottom (C), blade angle (φ), total liquid height (H/T), number of impeller blades (n_b) and blade thickness (t_b) were studied in detail. Power consumption was measured using a torque table

Power number was found to have a strong dependence on the flow pattern generated by the impeller. Unlike, DT and PTU, the power number of PTD was found to increase with a decrease in clearance. The PTD (T/3) was found to have the lowest power number in all the vessels and the power number increased with either a decrease or an increase in the impeller diameter from T/3. The dependence of power number on impeller diameter was found to be more prominent when the D/T ratio was more than 0.3. In general, the power number was found to increase with an increase in blade angle and blade width. The effect of blade width was found to be more prominent in larger diameter vessels. A correlation has been developed for power number in the case of PTD impellers.     

Memory Fault Modeling Trends: A Case Study

In recent years, embedded memories are the fastest growing segment of system on chip. They therefore have a major impact on the overall Defect per Million (DPM). Further, the shrinking technologies and processes introduce new defects that cause previously unknown faults; such faults have to be understood and modeled in order to design appropriate test techniques that can reduce the DPM level. This paper discusses a new memory fault class, namely dynamic faults, based on industrial test results; it defines the concept of dynamic faults based on the fault primitive concept. It further shows the importance of dynamic faults for the new memory technologies and introduces a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM on the table, and sets a direction for further research.